XC2C256

IC XC2C2566CP132C CPLD CoolRunner-II 256MC

CPLD - Complex Programmable Logic Devices / 132-CSPBGA (8x8)

XC2C256 IC XC2C2566CP132C CPLD CoolRunner-II 256MC

IC XC2C2566CP132C CPLD CoolRunner-II 256MC

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XC2C256

IC XC2C2566CP132C CPLD CoolRunner-II 256MC

CPLD - Complex Programmable Logic Devices / 132-CSPBGA (8x8)

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XC2C256 IC XC2C2566CP132C CPLD CoolRunner-II 256MC

Condição de XC2C256: novo em embalagem comercial

Outros Part Numbers para este componente: 2C256, XC2C256-6CP132C

The XC2C2566CP132C is a CPLD CoolRunner II Family 6K Gates 256 Macro Cells 256MHz 0.18um (CMOS) Technology 1.8V 132Pin CSBGA
132ball CP (0.5mm) BGA with 106 user I/O

The CoolRunnerII 256macrocell device is designed for both high performance and low power applications. This lends power savings to highend communication equipment and high speed to battery operated devices. Due to the low power standby and dynamic operation, overall system reliability is improved.

This device consists of sixteen Function Blocks interconnected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 Pterm PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.

Additionally, these registers can be globally reset or preset and configured as a D or T flipflop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pullup, open drain and programmable grounds. A Schmitttrigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as direct input registers to store signals directly from input pins.

Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clockenable, asynchronous set/reset and output enable signals can be formed using product terms on a permacrocell or perFunction Block basis.

A DualEDGE flipflop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device.

Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies.

The use of the clock divide (division by 2) and DualEDGE flipflop gives the resultant CoolCLOCK feature.

DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time.

Manufacturer:	Xilinx
Product Category:	CPLD Complex Programmable Logic Devices
Series:	XC2C256
Mounting Style:	SMD/SMT
Package / Case:	CSBGA132
Operating Supply Voltage:	1.8 V
Number of Macrocells:	256
Number of I/Os:	106 I/O
Supply Voltage Max:	1.9 V
Supply Voltage Min:	1.7 V
Minimum Operating Temperature:	0 C
Maximum Operating Temperature:	70 C
Maximum Operating Frequency:	256 MHz
Propagation Delay Max:	5.7 ns
Brand:	Xilinx
Number of Logic Array Blocks LABs:	16
Operating Supply Current:	21 uA
Product Type:	CPLD Complex Programmable Logic Devices
Subcategory:	Programmable Logic ICs